Study of optimized adder selection

In this paper, we propose a benchmark for an optimized adder selection. Adders can divide data into small groups which are interconnected by carry propagate units. These adders were synthesized with a Samsung 0.35 (μm), 3.3 V CMOS standard cell library while using design compiler. The CLA with which...

Full description

Saved in:
Bibliographic Details
Main Authors: Seok-Won Heo, Moon-Gyung Kim, Yong-Surk Lee
Format: Conference Proceeding
Language:English
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, we propose a benchmark for an optimized adder selection. Adders can divide data into small groups which are interconnected by carry propagate units. These adders were synthesized with a Samsung 0.35 (μm), 3.3 V CMOS standard cell library while using design compiler. The CLA with which small groups were synthesized with ungrouping is the fastest adder of all adders. It can operate at 289 MHz. The RCA with which all small groups were synthesized with grouping is the smallest adder of all adders. It has about 748.6 gates. The optimized adder for a crypto-processor is that of a 64-bit RCA based on 16-bit CLA. All small adder groups in this adder were synthesized with grouping. The adder can operate at a clock speed of 198.0 and has about 966.6. All adders can execute operations in the worst case conditions of 2.7 (V), 85 (°C).
ISSN:1523-553X
DOI:10.1109/ICASIC.2003.1277446