Methodology for on the fly partial reconfiguration for computation intensive applications on FPGA

As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an...

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Bibliographic Details
Main Authors: Bhandari, S, Pujari, S, Rai, A, Subbaraman, S
Format: Conference Proceeding
Language:English
Subjects:
Embedded systems
Field programmable gate arrays
Hardware
Hardware design languages
partial reconfiguration design methodology
Program processors
reconfigurable computing
Resource management
run time reconfiguration
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Summary:As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. The feature allows multiple functions to time-share the FPGA resources by exploiting reconfigurable area more efficiently. In such systems, one section of the FPGA continues to operate, while other section of the FPGA is disabled and partially reconfigured to provide new functionality. It is a vendor dependent feature. It is very useful feature where the required system needs to modify its functionality according to the need of the application. The paper describes PR, its types, supporting devices and the complete methodology to implement systems on reconfigurable hardware incorporating PR.
DOI:10.1109/ICCAIE.2010.5735004