A technique of optimal built-in self-test circuitries generation

The technique of generating an optimal built-in self-test (BIST) circuitries has been proposed. The technique is oriented on minimization of hardware overheads and dealt with automatization of BIST circuitries generation. The main idea consists in the use one test generator based on linear feedback...

Full description

Saved in:
Bibliographic Details
Main Authors: Chebykina, N V, Mosin, S G
Format: Conference Proceeding
Language:English
Subjects:
Binary sequences
Built-in self-test
Circuit faults
Design automation
Generators
Reliability
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The technique of generating an optimal built-in self-test (BIST) circuitries has been proposed. The technique is oriented on minimization of hardware overheads and dealt with automatization of BIST circuitries generation. The main idea consists in the use one test generator based on linear feedback shift register (LFSR) in two types of testing - pseudorandom and deterministic. The technique has been realized as CAD subsystems. The experimental results of technique application for some ISCAS'89 benchmark circuits have been shown.
DOI:10.1109/EWDTS.2010.5742133