10:4 MUX and 4:10 DEMUX gearbox LSI for 100-gigabit Ethernet link

The authors presents a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI implemented in 65nm CMOS decreases power dissipation by 75% compared to that of a conventional LSI.

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Bibliographic Details
Main Authors: Ono, G, Watanabe, K, Muto, T, Yamashita, H, Fukuda, K, Masuda, N, Nemoto, R, Suzuki, E, Takemoto, T, Yuki, F, Yagyu, M, Toyoda, H, Kambe, A, Saito, T, Nishimura, S
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS integrated circuits
Large scale integration
Phase locked loops
Power demand
Power dissipation
Voltage-controlled oscillators
Online Access:Request full text
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Description
Summary:The authors presents a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI implemented in 65nm CMOS decreases power dissipation by 75% compared to that of a conventional LSI.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2011.5746258