A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver

A 1.2 V 100 Mb/s 2.93 mW discrete-time charge-domain impulse radio ultra-wideband (IR-UWB) receiver is developed in 65 nm CMOS. In the charge-domain, the template of the correlator is represented by capacitance and the correlation is implemented by charge addition instead of voltage multiplication a...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2011-06, Vol.46 (6), p.1349-1359
Main Authors: Lechang Liu, Sakurai, T, Takamiya, M
Format: Article
Language:English
Subjects:
Applied sciences
auto-correlation
Capacitance
capacitance multiplier
charge-domain
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Clocks
Correlation
Correlators
cross-correlation
delay-locked loop
Design. Technologies. Operation analysis. Testing
Digital circuits
DLL
Electric potential
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Impulses
Integrated circuits
Oscillators, resonators, synthetizers
Phase locked loops
phase-locked loop
PLL
Receivers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Synchronism
Synchronization
Ultra-wideband
UWB
Voltage
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Summary:A 1.2 V 100 Mb/s 2.93 mW discrete-time charge-domain impulse radio ultra-wideband (IR-UWB) receiver is developed in 65 nm CMOS. In the charge-domain, the template of the correlator is represented by capacitance and the correlation is implemented by charge addition instead of voltage multiplication and voltage integration. Power consumption of the charge-domain receiver is minimized by a novel auto- and cross-correlation based synchronization scheme. To reduce the power consumption and the chip area of the PLL clock generator for the receiver, a dual charge-pump PLL is proposed to scale up the capacitance of the loop filter without extra charge-pump current. The developed UWB receiver with the area- and power-efficient PLL achieves the energy consumption of 29.3 pJ/bit with the 62.5-ps timing step for data synchronization.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2011.2128210