Partitioned bus-invert coding for power consumption optimization of data bus

For VLSI design in deep submicron technology, the bus energy reduction becomes more and more important. In this paper, we modify the bus-invert coding method to maximize the power consumption reduction of data bus. Unlike the conventional scheme in which the whole bus lines are considered for bus-in...

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Bibliographic Details
Main Authors: Junkai Sun, Anping Jiang
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Bus switching
Capacitance
Coding
Encoding
Hamming distance
Logic gates
Low power
Partitioned Bus-Invert coding
Power demand
Receivers
Switches
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Summary:For VLSI design in deep submicron technology, the bus energy reduction becomes more and more important. In this paper, we modify the bus-invert coding method to maximize the power consumption reduction of data bus. Unlike the conventional scheme in which the whole bus lines are considered for bus-invert coding, our scheme partitions the bus lines into several sub-buses and each partitioned sub-bus is coded independently by bus-invert coding method. For an 8-bit data bus the bus-invert coding method can reduce at least 25% power consumption, while the traditional bus-invert method is 18.75 %.
DOI:10.1109/ICCRD.2011.5764172