Scaleable Single-Photon Avalanche Diode Structures in Nanometer CMOS Technology

• Published in: IEEE transactions on electron devices 2011-07, Vol.58 (7), p.2028-2035
• Main Authors: Richardson, J A, Webster, E A G, Grant, L A, Henderson, R K
• Format: Article
• Language: English
• Subjects: Applied sciences; Biomedical imaging; CMOS integrated circuits; complementary metal-oxide-semiconductor (CMOS) integrated circuits; Compound structure devices; Design. Technologies. Operation analysis. Testing; Doping; Electric breakdown; Electronics; Exact sciences and technology; image sensors; Imaging devices; Implants; Integrated circuits; Junctions; Optoelectronic devices; p-n junctions; photodetectors; photodiodes; Pixel; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Tunneling
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2141138

Single-photon avalanche photodiodes (SPADs) operating in Geiger mode offer exceptional time resolution and optical sensitivity. Implementation in modern nanometer-scale complementary metal-oxide-semiconductor (CMOS) technologies to create dense high-resolution arrays requires a device structure that is scaleable down to a few micrometers. A family of three SPAD structures with sub-100-Hz mean dark count rate (DCR) is proposed in 130-nm CMOS image sensor technology. Based on a novel retrograde buried n-well guard ring, these detectors are shown to readily scale from 32 to 2 μm with improving DCR, jitter, and yield. One of these detectors is compatible with standard triple-well digital CMOS, and the others bring the first low-DCR realizations at the 130-nm node of shallow-trench-isolation-bounded and enhancement SPADs.