Synchronizer Performance in Deep Sub-Micron Technology

We show that the performance characteristics of synchronizer circuits track fabrication feature size reductions in a similar manner to the fan-out-of-four, FO4, inverter delay. We compare a variety of flip-flop circuit designs to a reference cross-coupled inverter circuit and show that flip-flops sp...

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Main Authors: Suwen Yang, Jones, I W, Greenstreet, M R
Format: Conference Proceeding
Language:English
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Asynchronous circuits
Metastability
Synchronizer
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Jones, I W
Greenstreet, M R
description We show that the performance characteristics of synchronizer circuits track fabrication feature size reductions in a similar manner to the fan-out-of-four, FO4, inverter delay. We compare a variety of flip-flop circuit designs to a reference cross-coupled inverter circuit and show that flip-flops specifically designed for synchronizer use outperform regular data path flip-flops with the progression of fabrication processes. However, care must be taken to compare circuits in each technology, because additional circuit features have often been added to flip-flop cells with each generation of process. These added features, for example to improve test coverage and facilitate clock selection, frequently degrade synchronizer performance. We present a new synchronizer circuit that performs almost as well as the cross-coupled inverter circuit and has reduced sensitivity to voltage supply variation.
doi_str_mv 10.1109/ASYNC.2011.19
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identifier ISSN: 1522-8681
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Asynchronous circuits
Metastability
Synchronizer
title Synchronizer Performance in Deep Sub-Micron Technology
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