Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits

This paper presents a built-in self-test/repair (BISTR) scheme for through-silicon via (TSV) based three-dimension integrated circuits (3D ICs). The proposed BIST structure focuses on the testing of a specific defective TSV by using a critical value of threshold. Then, the test results from BIST wil...

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Bibliographic Details
Main Authors: Hung-Yen Huang, Yu-Sheng Huang, Chun-Lung Hsu
Format: Conference Proceeding
Language:English
Subjects:
3D IC
area overhead
Benchmark testing
BISR
BIST
Built-in self-test
Maintenance engineering
Parallel processing
Three dimensional displays
Through-silicon vias
TSV
yield
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Summary:This paper presents a built-in self-test/repair (BISTR) scheme for through-silicon via (TSV) based three-dimension integrated circuits (3D ICs). The proposed BIST structure focuses on the testing of a specific defective TSV by using a critical value of threshold. Then, the test results from BIST will be delivered to the BISR structure for repairing the defective TSV. Additionally, a parallel processing approach is presented of the proposed BISTR scheme to speed up the operations of test and repair. Experimental results demonstrate that the proposed BISTR scheme can achieve the good performance in repair rate and yield with little area overhead penalty.
DOI:10.1109/APCCAS.2010.5774885