Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstr...

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Main Authors: Rahman, A, Agostinelli, M, Bai, P, Curello, G, Deshpande, H, Hafez, W, Jan, C.-H, Komeyli, K, Park, J, Phoa, K, Tsai, C, Yeh, J.-Y, Xu, J
Format: Conference Proceeding
Language:English
Subjects:
breakdown
BTI
CMOS
Degradation
Dielectrics
High-K dielectric
Integrated circuit reliability
Logic gates
metal gate
MOS devices
Reliability
SILC
SoC
TDDB
Transistors
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Summary:Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstrated. Importance of process optimizations to integrate robust I/O transistors without degrading performance and reliability of Logic transistors emphasized. Finally, Intrinsic and defect reliability monitoring for HVM are addressed.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2011.5784531