A CMOS low-power low-offset and high-speed fully dynamic latched comparator

This paper presents a novel dynamic latched comparator that demonstrates lower offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator,...

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Bibliographic Details
Main Authors: HeungJun Jeon, Yong-Bin Kim
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Delay
Inverters
Latches
Power demand
Threshold voltage
Transistors
Online Access:Request full text
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Summary:This paper presents a novel dynamic latched comparator that demonstrates lower offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage is improved. The complementary version of the regenerative latch stage, which provides larger output drive current than the conventional one at a limited area, is implemented. The proposed circuit is designed using 90 nm CMOS technology and 1 V power supply voltage, and it demonstrates up to 19% less offset voltage and 62% less sensitivity of the delay to the input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption.
ISSN:2164-1676
2164-1706
DOI:10.1109/SOCC.2010.5784646