An X86 microprocessor with multimedia extensions

• Main Authors: Draper, D.A., Crowley, M.P., Holst, J., Favor, G., Schoy, A., Ben-Meir, A., Trull, J., Khanna, R., Wendell, D., Krishna, R., Nolan, J., Partovi, H., Johnson, M., Lee, T., Mallick, D., Frydel, G., Vuong, A., Yu, S., Maley, R., Kauffmann, B.
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; Decoding; Filling; Hardware; History; Microprocessors; Out of order; Processor scheduling; Reduced instruction set computing; Registers
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.1997.585321

This sixth-generation X86 instruction-set compatible microprocessor implements a set of multimedia extensions. Instruction predecoding to identify instruction boundaries begins during filling of the 32 kB two-way set associative instruction cache after which the predecode bits are stored in the 20 kB predecode cache. The processor decodes up to two X86 instructions per clock, most of which are decoded by hardware into one to four RISC-like operations, called RISC86 Ops, whereas the uncommon instructions are mapped into ROM-resident RISC sequences. The instruction scheduler buffers up to 24 RISC86 operations, using register renaming with a total of 48 registers. Up to six RISC86 instructions are issued out-of-order to seven parallel execution units, speculatively executed and retired in order. The branch algorithm uses two-level branch prediction based on an 8192-entry branch history table, a 16-entry branch target cache and a 16-entry return address stack. The 10.18/spl times/15.38 mm/sup 2/ die contains 8.8M transistors. The chip is in 0.35 /spl mu/m CMOS using five layers of metal, shallow trench isolation, and tungsten local interconnect.