A CMOS mismatch model and scaling effects

In this letter a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model. The mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches. SPICE...

Full description

Saved in:
Bibliographic Details
Published in:IEEE electron device letters 1997-06, Vol.18 (6), p.261-263
Main Authors: Wong, Shyh-Chyi, Pan, Kuo-Hua, Ma, Dye-Jyun
Format: Article
Language:English
Subjects:
Analog circuits
Circuit simulation
Data mining
Immune system
MOS devices
Predictive models
Semiconductor device modeling
Semiconductor process modeling
SPICE
Threshold voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this letter a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model. The mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches. SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations. In addition, a /spl radic/n-law model is developed for modeling gate-finger dependence of mismatch.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.585349