32nm Embedded DRAM Reaching 400MHz and 0.1mm²/Mb on a Low Cost and Low Power Process

This paper presents an embedded DRAM memory design on 32 nm Low Power process using recently introduced Capacitor Over Low-K (COLK) bitcell architecture. It consists in the 1st functional silicon demonstration of 32 nm embedded DRAM macrocell with unrivalled density of O.lmmVMbit. The memory feature...

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Bibliographic Details
Main Authors: Vernet, M, Jeantet, O, Parashar, A, Degoirat, H, Verma, P K, Yadav, S K, Chawla, K, Atif, M, Handa, T, Sharad, S, Penaka, G P, Kundu, R, Nantet, S, Cremer, S, Goducheau, O
Format: Conference Proceeding
Language:English
Subjects:
Capacitors
Computer architecture
Driver circuits
Macrocell networks
Performance evaluation
Random access memory
Reliability
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Summary:This paper presents an embedded DRAM memory design on 32 nm Low Power process using recently introduced Capacitor Over Low-K (COLK) bitcell architecture. It consists in the 1st functional silicon demonstration of 32 nm embedded DRAM macrocell with unrivalled density of O.lmmVMbit. The memory features a high performance sense amplifier with tunable reference level, an overdriven reliability-friendly row decoder with adjusted voltage and a low swing although flexible data transfer scheme. Making low cost eDRAM with 2.5 ns cycle time available on 32 nm low power platform opens new opportunities for consumer electronics devices such as advanced smartphones or graphical handheld devices.
ISSN:2159-483X
DOI:10.1109/IMW.2011.5873202