Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

• Main Authors: Redolfi, A., Velenis, D., Thangaraju, S., Nolmans, P., Jaenen, P., Kostermans, M., Baier, U., Van Besien, E., Dekkers, H., Witters, T., Jourdan, N., Van Ammel, A., Vandersmissen, K., Rodet, S., Philipsen, H. G. G., Radisic, A., Heylen, N., Travaly, Y., Swinnen, B., Beyne, E.
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS integrated circuits; Copper; Fabrication; Silicon; Silicon carbide; Through-silicon vias
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2011.5898692

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O 3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.