Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration

• Main Authors: Ching-Kuan Lee, Tao-Chih Chang, Yu-Jiau Huang, Huan-Chun Fu, Jui-Hsiung Huang, Zhi-Cheng Hsiao, Lau, J. H., Cheng-Ta Ko, Ren-Shin Cheng, Pei-Chen Chang, Kuo-Shu Kao, Yu-Lan Lu, Lo, R., Kao, M. J.
• Format: Conference Proceeding
• Language: English
• Subjects: Aging; Assembly; Bonding; Copper; Reliability; Scanning electron microscopy; Tin
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2011.5898704

In this investigation, Cu/Sn lead-free solder microbumps with 10 μm pads on 20 μm pitch are designed and fabricated. The chip size is 5mm × 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (-55⇆125°C, dwell and ramp times = 15 min). Finally, ultra fine-pitch (5μm pads on 10μm pitch) lead-free solder microbumping is explored.