Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time

• Main Authors: Amory, A. M., Marcon, C. A. M., Moraes, F. G., Lubaszewski, M. S.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuit faults; Delay; Energy consumption; Equations; execution time; Mathematical model; MPSoC; Reliability; task mapping; Tiles; yield
• ISSN: 2150-5500; 2150-5519
• DOI: 10.1109/RSP.2011.5929991

The use of spare tiles in a networks-on-chip based multi-processor chip can improve the yield, reducing the cost of the chip and maintaining the system functionality even if the chip is defective. However, the impact of this approach on application characteristics, such as energy consumption and execution time, is not documented. For instance, on one hand the application tasks might be mapped onto any tile of a defect-free chip. On the other hand, a chip with a defective tile needs special task mapping that avoid fault tiles. This paper presents a task mapping aware of faulty tiles, where an alternative task mapping can be generated and evaluated in terms of energy consumption and execution time. The results show that faults on tiles have, on average, a small effect on energy consumption but no significant effect on execution time. It demonstrates that spare tiles can improve yield with a small impact on the application requirements.