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A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based \Sigma \Delta Modulator
A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes t...
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Published in: | IEEE journal of solid-state circuits 2011-09, Vol.46 (9), p.2084-2098 |
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container_end_page | 2098 |
container_issue | 9 |
container_start_page | 2084 |
container_title | IEEE journal of solid-state circuits |
container_volume | 46 |
creator | Elsayed, M. M. Dhanasekaran, V. Gambhir, M. Silva-Martinez, J. Sanchez-Sinencio, E. |
description | A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the ΣΔ modulator, emulating the voltage-DAC in a conventional ΣΔ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the ΣΔ-modulator achieves a dynamic range of 68 dB and the TDC consumes 5.66 mW at 250 MHz event rate while occupying 0.006 mm 2 . |
doi_str_mv | 10.1109/JSSC.2011.2156990 |
format | article |
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M. ; Dhanasekaran, V. ; Gambhir, M. ; Silva-Martinez, J. ; Sanchez-Sinencio, E.</creator><creatorcontrib>Elsayed, M. M. ; Dhanasekaran, V. ; Gambhir, M. ; Silva-Martinez, J. ; Sanchez-Sinencio, E.</creatorcontrib><description>A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the ΣΔ modulator, emulating the voltage-DAC in a conventional ΣΔ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. 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Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the ΣΔ modulator, emulating the voltage-DAC in a conventional ΣΔ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the ΣΔ-modulator achieves a dynamic range of 68 dB and the TDC consumes 5.66 mW at 250 MHz event rate while occupying 0.006 mm 2 .</description><subject>DAC</subject><subject>Delay</subject><subject>Inverters</subject><subject>mixed signal circuits</subject><subject>Pulse width modulation</subject><subject>Sigma \Delta ADC</subject><subject>Signal resolution</subject><subject>Signal to noise ratio</subject><subject>TDC</subject><subject>time-mode</subject><subject>Time-to-digital</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><recordid>eNo9kN1Kw0AQhRdRsFYfQLyZF9i4k938Xda0WqW1YCp6UQjbZFIj-SmbtahPb0qLc3MYZs6Z4WPsGoWDKKLbpySJHVcgOi56fhSJEzZAzws5BvL9lA2EwJBHrhDn7KLrPvtWqRAH7HsEwglh28H4eQbLsiZuWz4uN6XVFcRtsyNjycBbaT_A9QTMp78w2VFj4UVbgrIB34Omhni-SKBozSFj3ubE73RHOaySclNrWI2pshr6wVelbWsu2Vmhq46ujjpkr_eTZTzls8XDYzya8cz1PctJY6ik8FWBayLKcykj2atUOguKddFX4KKPUgsfM6UEqSLIw0gL6VMQrOWQ4SE3M23XGSrSrSlrbX5SFOkeXbpHl-7RpUd0vefm4Cn7k__7XiSV7J_5A8FQaBk</recordid><startdate>201109</startdate><enddate>201109</enddate><creator>Elsayed, M. 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M.</creatorcontrib><creatorcontrib>Dhanasekaran, V.</creatorcontrib><creatorcontrib>Gambhir, M.</creatorcontrib><creatorcontrib>Silva-Martinez, J.</creatorcontrib><creatorcontrib>Sanchez-Sinencio, E.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Elsayed, M. M.</au><au>Dhanasekaran, V.</au><au>Gambhir, M.</au><au>Silva-Martinez, J.</au><au>Sanchez-Sinencio, E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based \Sigma \Delta Modulator</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2011-09</date><risdate>2011</risdate><volume>46</volume><issue>9</issue><spage>2084</spage><epage>2098</epage><pages>2084-2098</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the ΣΔ modulator, emulating the voltage-DAC in a conventional ΣΔ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the ΣΔ-modulator achieves a dynamic range of 68 dB and the TDC consumes 5.66 mW at 250 MHz event rate while occupying 0.006 mm 2 .</abstract><pub>IEEE</pub><doi>10.1109/JSSC.2011.2156990</doi><tpages>15</tpages></addata></record> |
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language | eng |
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subjects | DAC Delay Inverters mixed signal circuits Pulse width modulation Sigma \Delta ADC Signal resolution Signal to noise ratio TDC time-mode Time-to-digital |
title | A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based \Sigma \Delta Modulator |
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