An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm circuits and beyond. An on-chip metastability measurement circuit was fabricated in a 65nm 1.1V bulk CMOS. A fully digital on-chip measurement...

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Main Authors: Beer, Salomon, Ginosar, Ran, Priel, Michael, Dobkin, Rostislav, Kolodny, Avinoam
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Frequency measurement
Latches
Libraries
Logic gates
Semiconductor device measurement
Synchronization
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creator Beer, Salomon
Ginosar, Ran
Priel, Michael
Dobkin, Rostislav
Kolodny, Avinoam
description Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm circuits and beyond. An on-chip metastability measurement circuit was fabricated in a 65nm 1.1V bulk CMOS. A fully digital on-chip measurement system is presented here that helps to characterize synchronizers in future technologies. Different types of synchronizers were measured and compared. The standard library FF is demonstrated to have lower tau value than various feedback flip-flops.
doi_str_mv 10.1109/ISCAS.2011.5938135
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subjects Clocks
Frequency measurement
Latches
Libraries
Logic gates
Semiconductor device measurement
Synchronization
title An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm
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