Electrical performances of low resistive W buried gate using B2H6-reduced W nucleation layer technology for 30nm-based DRAM devices

• Main Authors: Choon-Hwan Kim, Il-Cheol Rho, Byung-Soo Eun, Hyun-Phill Kim, Sung-gon Jin, Hyo-Sang Kang
• Format: Conference Proceeding
• Language: English
• Subjects: Conductivity; Grain size; Logic gates; Random access memory; Resistance; Transistors
• ISSN: 2380-632X; 2380-6338
• DOI: 10.1109/IITC.2011.5940358

Low resistive tungsten (W) interconnects using chemical vapor deposited W (CVD-W) films deposited on B 2 H 6 -reduced W nucleation layers have been successfully developed for the buried gate electrode of sub-30nm dynamic random access memory (DRAM). The low resistive W film showed excellent gap fill performance and larger grain size than that of the conventional CVD-W film at the 30nm shallow trench pattern. The gate resistance of low resistive W film was ~25% reduced even at the 30nm trench pattern, which is due to the larger grain at the shallow trench. In addition, the gate oxide integrity and reliability were drastically improved, compared to the conventional CVD-W buried gate. However, the properties of transistor including saturation threshold voltage (Vt sat ) and saturation drain current (Id sat ) were degraded due to the penetration of boron into channel at the B 2 H 6 -reduced W nucleation layer. In order to adjust the transistor characteristics, the optimization of channel implantation condition is suggested.