A parallel pipelined DSP processor core

In this paper a novel high performance processor is presented along with its applicability to digital signal processing. The generic sum of product processor organization contains three major sections: parallel, reduction, and multifunction generator. Each of these sections works in a pipelined fash...

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Bibliographic Details
Main Authors: Aikens, V.C., Delgado-Frias, J.G., Pechanek, G.G., Vassiliadis, S.
Format: Conference Proceeding
Language:English
Subjects:
Convolution
Delay
Digital signal processing
Discrete Fourier transforms
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Hardware
Microelectronics
Multiplexing
Parallel processing
Signal processing algorithms
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Summary:In this paper a novel high performance processor is presented along with its applicability to digital signal processing. The generic sum of product processor organization contains three major sections: parallel, reduction, and multifunction generator. Each of these sections works in a pipelined fashion providing extremely high performance. We have studied a number of digital signal processing algorithms and mapped them onto the proposed processor. We report the mapping of three of the most widely used algorithms: convolution, discrete Fourier transform, and discrete cosine transform. In order to evaluate the potential impact of the processor, we have included a performance comparison with other digital signal processing machines. The proposed processor performs extremely well using a small amount of hardware.
DOI:10.1109/MWSCAS.1996.594039