A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS

A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinear...

Full description

Saved in:
Bibliographic Details
Main Authors: Ghahramani, M. M., Ferriss, M. A., Flynn, M. P.
Format: Conference Proceeding
Language:English
Subjects:
Delta-sigma
Detectors
fractional-N
Frequency shift keying
MSK
Phase locked loops
phase-locked loop
synthesizer
Transmitters
Voltage-controlled oscillators
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinearity associated with some TDC-based digital PLLs. The prototype achieves an MSK modulation rate of 2Mb/s, delivers -2dBm of output power, and is free of in-band fractional spurs. The transmitter, implemented in 130nm CMOS, consumes 17mW from a 1.2V supply and occupies an active area of 0.6mm 2 .
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2011.5940590