FPGA implementation of a pipelined 2D-DCT and simplified quantization for real-time applications

• Main Authors: Anas, H., Belkouch, S., El Aakif, M., Chabini, N.
• Format: Conference Proceeding
• Language: English
• Subjects: Discret cosine transform; Discrete cosine transforms; Field programmable gate arrays; FPGA; Image coding; JPEG Compression; PSNR; Quantization; Transform coding
• DOI: 10.1109/ICMCS.2011.5945659

The Discrete Cosine Transform (DCT) is one of the most widely used techniques for image compression. Several algorithms are proposed to implement the DCT-2D. The scaled SDCT algorithm is an optimization of the DCT-1D, which consists in gathering all the multiplications at the end. In this paper, in addition to the hardware implementation on an FPGA, an extended optimization has been performed by merging the multiplications in the quantization block without having an impact on the image quality. Tests using MATLAB environment have shown that our proposed approach produces images with quality comparable to the ones obtained using the JPEG standard. FPGA-based implementations of this proposed approach and the Loeffler's algorithm are proposed and compared in this paper using an Altera Startix FPGA family with the synthesis and implementation tool Quartus II. Results show that our approach outperforms the well known Loeffler's algorithm in terms of processing-speed and resources used.