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A Scalable Massively Parallel Processor for Real-Time Image Processing

This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high pe...

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Published in:IEEE journal of solid-state circuits 2011-10, Vol.46 (10), p.2363-2373
Main Authors: Kurafuji, T., Haraguchi, M., Nakajima, M., Nishijima, T., Tanizaki, T., Yamasaki, H., Sugimura, T., Imai, Y., Ishizaki, M., Kumaki, T., Murata, K., Yoshida, K., Shimomura, E., Noda, H., Okuno, Y., Kamijo, S., Koide, T., Mattausch, H. J., Arimoto, K.
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cited_by cdi_FETCH-LOGICAL-c295t-15d2877915c2be621af3ef706375949c3dd43356d02a31047e4348c806cf6d9d3
cites cdi_FETCH-LOGICAL-c295t-15d2877915c2be621af3ef706375949c3dd43356d02a31047e4348c806cf6d9d3
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container_issue 10
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container_title IEEE journal of solid-state circuits
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creator Kurafuji, T.
Haraguchi, M.
Nakajima, M.
Nishijima, T.
Tanizaki, T.
Yamasaki, H.
Sugimura, T.
Imai, Y.
Ishizaki, M.
Kumaki, T.
Murata, K.
Yoshida, K.
Shimomura, E.
Noda, H.
Okuno, Y.
Kamijo, S.
Koide, T.
Mattausch, H. J.
Arimoto, K.
description This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high performance of 191 GOPS, a high power efficiency of 310 GOPS/W, and a high area efficiency of 31.6 GOPS/mm 2 . The applied pipeline architecture is optimized to reduce the number of controller overhead cycles so that the SIMD parallel processing unit can be utilized during up to 99% of the operating time of typical application programs. The processor can be also optimized for low cost, low power, and high performance multimedia system-on-a-chip (SoC) solutions. A combination of custom and automated implementation techniques enables scalability in the number of PEs. The processor has two operating modes, a normal frequency (NF) mode for higher power efficiency and a double frequency (DF) mode for higher performance. The combination of high area efficiency, high power efficiency, high performance, and the flexibility of the SIMD processor described in this paper expands the application of real-time image processing technology to a variety of electronic devices.
doi_str_mv 10.1109/JSSC.2011.2159528
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identifier ISSN: 0018-9200
ispartof IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2363-2373
issn 0018-9200
1558-173X
language eng
recordid cdi_ieee_primary_5954135
source IEEE Xplore (Online service)
subjects Adders
Applied sciences
area efficiency
Cross-disciplinary physics: materials science
rheology
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
fine grained processing element
Image processing
Image processor
Integrated circuits
Integrated circuits by function (including memories and processors)
Materials science
Physics
Pipelines
Porous materials
granular materials
power efficiency
Process control
Random access memory
Real time systems
Registers
scalable architecture
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
SIMD
Specific materials
title A Scalable Massively Parallel Processor for Real-Time Image Processing
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