Yield model for ASIC and processor chips

Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of ch...

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Bibliographic Details
Main Authors: Stapper, C.H., Patrick, J.A., Rosner, R.J.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Area measurement
CMOS logic circuits
CMOS process
CMOS technology
Logic circuits
Manufacturing
Microprocessors
Semiconductor device measurement
Semiconductor device modeling
Online Access:Request full text
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Description
Summary:Yield models based on chip area are inadequate for modeling the yield of CMOS ASIC and processor chips. A model based on the number of circuits was found to give more accurate results. Defect learning curves measured with DRAMs have been used successfully to project the yield of a wide variety of chips.
ISSN:1550-5774
2377-7966
DOI:10.1109/DFTVS.1993.595739