Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce...

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Bibliographic Details
Main Authors: Blom, F., Oliver, J., Rullan, M., Ferrer, C.
Format: Conference Proceeding
Language:English
Subjects:
Circuit faults
Circuit testing
Degradation
Design for testability
Fault detection
Libraries
Semiconductor device modeling
Switching circuits
System testing
Very large scale integration
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Description
Summary:The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells.
ISSN:1550-5774
2377-7966
DOI:10.1109/DFTVS.1993.595782