Hierarchical 2-D Field Solution For Capacitance Extraction For VLSI Interconnect Modeling

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Bibliographic Details
Main Authors: Dengi, E.A., Rohrer, R.A.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Conductors
Delay systems
Dielectrics
Integrated circuit interconnections
Integrated circuit technology
Libraries
Permission
Semiconductor device modeling
Very large scale integration
Online Access:Request full text
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ISSN:0738-100X
DOI:10.1109/DAC.1997.597130