Cost efficient codesign for JPEG system

In this paper, we propose an improved hardware-software codesign methodology for implementation on embedded system. The codesign flow begins with profiling of the system algorithm. With the analysis of profiling, constraint of computation requirement for the application system, and the provided soft...

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Bibliographic Details
Main Authors: Hun-Chen Chen, Jui-Cheng Yen, Chien-Wan Hun, Po-Wei Huang, Hung-Chun Chen
Format: Conference Proceeding
Language:English
Subjects:
Complexity theory
Discrete cosine transforms
Embedded systems
Hardware
Silicon
Transform coding
Online Access:Request full text
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Summary:In this paper, we propose an improved hardware-software codesign methodology for implementation on embedded system. The codesign flow begins with profiling of the system algorithm. With the analysis of profiling, constraint of computation requirement for the application system, and the provided software-hardware resources on the specific embedded system platform, we partition the application system and allocate the system blocks on the embedded system with software and hardware resources to be a high performance codesign. For high efficient allocation of the system blocks, we created a cost-efficiency function to evaluate the efficiency of software and hardware on the implementation of the embedded system. In our study, a JPEG system is verified on the specific embedded system with the proposed codesign methodology. To achieve high efficient implementation on the specific embedded system platform, reducing the code size and hardware cost are the main tasks. Thus, low computation complexity and low hardware cost DCT/IDCT IPs are also proposed in this paper. Comparing with the design with pure software, the throughput of hardware-software codesign is 1.6 times of it. The cost-efficiency is improved around 1.715 times.
ISSN:0747-668X
2159-1423
DOI:10.1109/ISCE.2011.5973880