Cost reduction on high-speed 1D IDCT architecture based on time rescaling

In this paper, high-speed IDCT/DCT architectures based on B.G Lee's fast IDCT/DCT algorithm are investigated by pipelining and the systolic structure is proposed for hardware reduction applying to high speed IDCT/DCT structures based on time rescaling. Pipelining enables the high speed of struc...

Full description

Saved in:
Bibliographic Details
Main Authors: Yu-Chi Tsao, Ken Choi
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Computer architecture
Delay
digital signal processing (DSP)
Discrete cosine transforms
Hardware
High-speed 1D IDCT/DCT architecture
Pipeline processing
pipelining
time rescaling
Very large scale integration
VLSI
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, high-speed IDCT/DCT architectures based on B.G Lee's fast IDCT/DCT algorithm are investigated by pipelining and the systolic structure is proposed for hardware reduction applying to high speed IDCT/DCT structures based on time rescaling. Pipelining enables the high speed of structures but it also causes costly increase on hardware consumption over the original architectures from additional delay elements. On the other hand, multipliers are the most expensive components within IDCT/DCT architecture due to highly cost of area in terms of VLSI implementation. In this paper, we first investigate the interrelationship among IDCT/DCT structures with different pipelining stages. Secondly, a systolic element enabling multiplier reuse based on time rescaling is presented, which eliminates redundant duplicate multipliers within IDCT/DCT architecture and therefore the required hardware cost, namely area, of high-speed IDCT/DCT structures can be vastly saved.
ISSN:2154-0357
2154-0373
DOI:10.1109/EIT.2011.5978572