Mode detection of a linear-logarithmic current-mode image sensor

A current-mode column readout circuit architecture is presented. The readout circuit is composed of a first-generation current conveyor, a current memory employed as a delta reset sampling unit, a differential amplifier as an integrator and a dynamic comparator. The current-mode active pixel sensor...

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Bibliographic Details
Main Authors: Khamsehashari, E., Audet, Y.
Format: Conference Proceeding
Language:English
Subjects:
Active Pixel Sensor (APS)
Capacitors
Computer architecture
Current Comparator (CMP)
Delta Reset Sampling (DRS)
Dynamic range
Image sensors
Microprocessors
Noise
Transistors
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Description
Summary:A current-mode column readout circuit architecture is presented. The readout circuit is composed of a first-generation current conveyor, a current memory employed as a delta reset sampling unit, a differential amplifier as an integrator and a dynamic comparator. The current-mode active pixel sensor uses a PMOS readout transistor in the linear region of operation and a PMOS reset transistor that allows for a linear-logarithmic response. The pixel response operation is determined in the column readout circuit and a signal is sent to the digital processing unit as an indicator. Experimental results, obtained from test structure, are presented. The circuit was fabricated in a CMOS 0.35um process from Austria Microsystems.
DOI:10.1109/NEWCAS.2011.5981203