Single Electron Transistor analytical model for hybrid circuit design

A novel analytical and compact model of Single Electron Transistor (SET) is developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design. The model is based on the steady state Master-Equation (ME). The implementation of this original and simple model, taking into...

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Bibliographic Details
Main Authors: Bounouar, M. A., Calmon, F., Beaumont, A., Guilmain, M., Xuan, W., Ecoffey, S., Drouin, D.
Format: Conference Proceeding
Language:eng ; jpn
Subjects:
Analytical models
CMOS integrated circuits
Coulomb Blockade
Hybrid SET-CMOS circuit design
Integrated circuit modeling
Junctions
Logic gates
Semiconductor device modeling
SET modeling
Single Electron Transistor (SET)
Tunneling
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Description
Summary:A novel analytical and compact model of Single Electron Transistor (SET) is developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design. The model is based on the steady state Master-Equation (ME). The implementation of this original and simple model, taking into account physical characteristics of tunnel junctions and the thermionic emission, has faithfully reproduced the behavior of metallic SET operating at room temperature. The hybrid SET-CMOS universal logic gate cell is analyzed to illustrate the efficiency of this compact SET model.
DOI:10.1109/NEWCAS.2011.5981330