Modeling the effect of parasitic capacitances on the dead-time distortion in multilevel NPC inverters

A simple model is derived and verified for evaluating the effect of parasitic capacitances on the dead-time related voltage distortion in multilevel NPC voltage source inverters. The model permits well-defined and precise compensation of dead-time distortion, exhibiting meaningful improvement on com...

Full description

Saved in:
Bibliographic Details
Main Authors: Szwarc, Krzysztof Jakub, Cichowski, A., Nieznanski, J., Szczepankowski, P.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
dead time compensation
Harmonic analysis
Inverters
Leg
Modulation
Multilevel inverters
Switching circuits
Transistors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A simple model is derived and verified for evaluating the effect of parasitic capacitances on the dead-time related voltage distortion in multilevel NPC voltage source inverters. The model permits well-defined and precise compensation of dead-time distortion, exhibiting meaningful improvement on compensation methods neglecting the effects of parasitic capacitances. A simple formula is given for evaluating the capacitances as serial/parallel connections of transistor capacitances and external capacitances (introduced by the cables and load).
ISSN:2163-5137
DOI:10.1109/ISIE.2011.5984442