A 28nm poly/SiON CMOS technology for low-power SoC applications

This paper presents a state-of-the-art 28 nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class transistor performance, SRAM SNM (static noise margin), MOM capacitance density and mismatch, and ULK (k = 2.5) interconnect. The ION are 683 and 503...

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Main Authors: Liang, C. W., Chen, M. T., Jenq, J. S., Lien, W. Y., Huang, C. C., Lin, Y. S., Tzau, B. J., Wu, W. J., Fu, Z. H., Wang, I. C., Chou, P. Y., Fu, C. S., Tzeng, C. Y., Chiu, K. L., Huang, L. S., You, J. W., Hung, J. G., Cheng, Z. M., Hsu, B. C., Wang, H. Y., Ye, Y. H., Wu, J. Y., Yang, C. L., Chien, C. C., Wang, Y. R., Liu, C. C., Tzou, S. F., Huang, Y. H., Yu, C. C., Liao, J. H., Lin, C. L., Chen, D. F., Chien, S. C., Chen, I. C.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Copper
Logic gates
Moment methods
Random access memory
Reliability
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Summary:This paper presents a state-of-the-art 28 nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class transistor performance, SRAM SNM (static noise margin), MOM capacitance density and mismatch, and ULK (k = 2.5) interconnect. The ION are 683 and 503 uA/um (at I OFF = 1 nA/um, V DD =1 V) for the n- and p-MOSFET, respectively. (With normalized t OX and V DD , these values are higher than prior publication by 5%/15%). The 6T-SRAM is aggressively scaled to
ISSN:0743-1562