Gallium-Incorporated TiN Metal Gate With Band-Edge Work Function and Excellent Thermal Stability for PMOS Device Applications

• Published in: IEEE electron device letters 2011-09, Vol.32 (9), p.1197-1199
• Main Authors: Xu, Qiuxia, Xu, Gaobo, Liang, Qingqing, Yao, Yuan, Duan, Xiaofeng, Li, Junfeng
• Format: Article
• Language: English
• Subjects: Applied sciences; Band-edge work function; Capacitors; Condensed matter: electronic structure, electrical, magnetic, and optical properties; Devices; Electronic structure and electrical properties of surfaces, interfaces, thin films and low-dimensional structures; Electronics; Exact sciences and technology; Gallium; gallium-incorporated TiN metal gate; Gates; HfLaON dielectric; Logic gates; MOSFETs; Physics; PMOS device; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon dioxide; Stacks; Surface double layers, schottky barriers, and work functions; Thermal stability; Tin; Transistors; Work functions
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2011.2160147

A cost-effective method for modulating the effective work function (EWF) of a metal gate while simultaneously decreasing the equivalent oxide thickness (EOT) of a high- k dielectric is proposed for the first time. By incorporating gallium (Ga) into the TiN/HfLaON/interfacial layer (IL) SiO 2 PMOS gate stack, a band-edge EWF of 5.18 eV and an EOT of 0.57 nm can be obtained. Excellent thermal stability was maintained even after the post metal anneal (PMA) at 1000°C. The impacts of TiN thickness, Ga implant doses, and PMA conditions on the properties of the Ga-incorporated TiN/HLaON/IL SiO 2 gate stack are investigated, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the gate-first process flow to fabricate PMOSFETs with a minimum gate length of 28 nm.