Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study

• Main Authors: Portela-Garcia, M., Lindoso, A., Entrena, L., Garcia-Valderas, M., Lopez-Ongil, C., Pianta, B., Poehls, L. B., Vargas, F.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuit faults; Dictionaries; Embedded Software Design; Fault injection; Optimization; Pipelines; Robustness; SET; SEU; Single event upset; Software
• ISSN: 2373-0862
• DOI: 10.1109/LATW.2011.5985918

Microprocessor-based system's robustness under Single Event Effects is a very current concern. A widely adopted solution to make robust a microprocessor-based system consists in modifying the software application by adding redundancy and fault detection capabilities. The efficiency of the selected software-based solution must be assessed. This evaluation process allows the designers to choose the more suitable robustness technique and check if the hardened system achieves the expected dependability levels. Several approaches with this purpose can be found in the literature, but their efficiency is limited in terms of the number of faults that can be injected, as well as the level of accuracy of the fault injection process. In this paper, we propose FPGA-based fault injection techniques to evaluate software robustness methods under Single Event Upset (SEU) as well as Single Event Transient (SET). Experimental results illustrate the benefits of using the proposed fault injection method, which is able to evaluate a high amount of faults of both types of events.