Nano-scale Si-capping thicknesses impacting junction performance on silicon substrate

Silicon capping layer is a useful dielectric smoothing the interface integrity between gate dielectric and SiGe deposition layer in nano-scale process technology and reducing the possibility of Ge atom diffusion into the gate dielectric. However, the junction performance in reverse saturation curren...

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Bibliographic Details
Main Authors: Mu-Chun Wang, Ren-Hau Yang, Wen-Shiang Liao, Hsin-Chia Yang, Yi-Jhen Li, Heng-Sheng Huang
Format: Conference Proceeding
Language:English
Subjects:
capping layer
CESL
Dielectrics
IP networks
junction leakage
Junctions
Logic gates
MOSFET
MOSFET circuits
Silicon
Strain
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Summary:Silicon capping layer is a useful dielectric smoothing the interface integrity between gate dielectric and SiGe deposition layer in nano-scale process technology and reducing the possibility of Ge atom diffusion into the gate dielectric. However, the junction performance in reverse saturation current is suffered. Through the deliberate pattern design, the fringe junction leakage for MOSFET device was effectively extracted. The thicker Si capping layer well prevents Ge atom from diffusing into gate dielectric, but causes more fringe junction leakage at source/drain sites.
ISSN:2159-3523
DOI:10.1109/INEC.2011.5991637