Loading…
A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths
The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology fo...
Saved in:
Main Authors: | , , |
---|---|
Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 295 |
container_issue | |
container_start_page | 290 |
container_title | |
container_volume | |
creator | Ram, D. S. H. Bhuvaneswari, M. C. Logesh, S. M. |
description | The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology for area, power and delay optimization using the Non-dominated Sorting Genetic Algorithm II (NSGA II). A metric based technique has been used to determine the likelihood of a schedule to yield low power solutions during binding. Actual power numbers are not determined since this is computationally expensive. The methodology has been evaluated on standard benchmark Data-Flow Graphs (DFGs) and results indicate that it yields improved solutions with better diversity when compared to a weighted sum GA approach. For the IIR benchmark, it was observed that the NSGA II was able to converge to the true Pareto front obtained from exhaustive search. |
doi_str_mv | 10.1109/ISVLSI.2011.55 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5992521</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5992521</ieee_id><sourcerecordid>5992521</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-152f153bcd5b9740ec948d3f76460d7d483179ae55527bfa8a6ebad9941f78b83</originalsourceid><addsrcrecordid>eNo9z81OwkAUhuHxLxGRrRs35wIszm-nsySCQlLFBHRLpu2pHVJabAcMXL2gxtW3eJI3-Qi5YbTPGDX3k9l7PJv0OWWsr9QJ6RkdUR0aJaXU_JR0OFMmEFLrsx9jUmlNIyrM-b-F5pJcte2SUnFw3iH7AbzUWyxhtK3LjXd1ZZsdzDEtKve5QcjrBp43pXdBnSwx9W6L8Fp_YXMHgwYt2CqDIZZ2B9O1dyu3t8cGuArG7qOAGI_t2a7yBbauhTqHofV2bX3RXpOL3JYt9v62S94eR_OHcRBPnyYPgzhwTCsfMMVzpkSSZioxWlJMjYwyketQhjTTmYwE08aiUorrJLeRDTGxmTGS5TpKItElt79dh4iLdeNWh4sLZQxXnIlvPXdijQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Ram, D. S. H. ; Bhuvaneswari, M. C. ; Logesh, S. M.</creator><creatorcontrib>Ram, D. S. H. ; Bhuvaneswari, M. C. ; Logesh, S. M.</creatorcontrib><description>The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology for area, power and delay optimization using the Non-dominated Sorting Genetic Algorithm II (NSGA II). A metric based technique has been used to determine the likelihood of a schedule to yield low power solutions during binding. Actual power numbers are not determined since this is computationally expensive. The methodology has been evaluated on standard benchmark Data-Flow Graphs (DFGs) and results indicate that it yields improved solutions with better diversity when compared to a weighted sum GA approach. For the IIR benchmark, it was observed that the NSGA II was able to converge to the true Pareto front obtained from exhaustive search.</description><identifier>ISSN: 2159-3469</identifier><identifier>ISBN: 9781457708039</identifier><identifier>ISBN: 1457708035</identifier><identifier>EISSN: 2159-3477</identifier><identifier>EISBN: 9780769544472</identifier><identifier>EISBN: 0769544479</identifier><identifier>DOI: 10.1109/ISVLSI.2011.55</identifier><language>eng</language><publisher>IEEE</publisher><subject>Behavioral synthesis ; Benchmark testing ; Biological cells ; Delay ; evolutionary computation ; Genetic algorithms ; high-level synthesis ; low power design ; multi-objective optimization ; Optimization ; Schedules ; System level design</subject><ispartof>2011 IEEE Computer Society Annual Symposium on VLSI, 2011, p.290-295</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5992521$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54530,54895,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5992521$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ram, D. S. H.</creatorcontrib><creatorcontrib>Bhuvaneswari, M. C.</creatorcontrib><creatorcontrib>Logesh, S. M.</creatorcontrib><title>A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths</title><title>2011 IEEE Computer Society Annual Symposium on VLSI</title><addtitle>isvlsi</addtitle><description>The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology for area, power and delay optimization using the Non-dominated Sorting Genetic Algorithm II (NSGA II). A metric based technique has been used to determine the likelihood of a schedule to yield low power solutions during binding. Actual power numbers are not determined since this is computationally expensive. The methodology has been evaluated on standard benchmark Data-Flow Graphs (DFGs) and results indicate that it yields improved solutions with better diversity when compared to a weighted sum GA approach. For the IIR benchmark, it was observed that the NSGA II was able to converge to the true Pareto front obtained from exhaustive search.</description><subject>Behavioral synthesis</subject><subject>Benchmark testing</subject><subject>Biological cells</subject><subject>Delay</subject><subject>evolutionary computation</subject><subject>Genetic algorithms</subject><subject>high-level synthesis</subject><subject>low power design</subject><subject>multi-objective optimization</subject><subject>Optimization</subject><subject>Schedules</subject><subject>System level design</subject><issn>2159-3469</issn><issn>2159-3477</issn><isbn>9781457708039</isbn><isbn>1457708035</isbn><isbn>9780769544472</isbn><isbn>0769544479</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9z81OwkAUhuHxLxGRrRs35wIszm-nsySCQlLFBHRLpu2pHVJabAcMXL2gxtW3eJI3-Qi5YbTPGDX3k9l7PJv0OWWsr9QJ6RkdUR0aJaXU_JR0OFMmEFLrsx9jUmlNIyrM-b-F5pJcte2SUnFw3iH7AbzUWyxhtK3LjXd1ZZsdzDEtKve5QcjrBp43pXdBnSwx9W6L8Fp_YXMHgwYt2CqDIZZ2B9O1dyu3t8cGuArG7qOAGI_t2a7yBbauhTqHofV2bX3RXpOL3JYt9v62S94eR_OHcRBPnyYPgzhwTCsfMMVzpkSSZioxWlJMjYwyketQhjTTmYwE08aiUorrJLeRDTGxmTGS5TpKItElt79dh4iLdeNWh4sLZQxXnIlvPXdijQ</recordid><startdate>201107</startdate><enddate>201107</enddate><creator>Ram, D. S. H.</creator><creator>Bhuvaneswari, M. C.</creator><creator>Logesh, S. M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201107</creationdate><title>A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths</title><author>Ram, D. S. H. ; Bhuvaneswari, M. C. ; Logesh, S. M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-152f153bcd5b9740ec948d3f76460d7d483179ae55527bfa8a6ebad9941f78b83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Behavioral synthesis</topic><topic>Benchmark testing</topic><topic>Biological cells</topic><topic>Delay</topic><topic>evolutionary computation</topic><topic>Genetic algorithms</topic><topic>high-level synthesis</topic><topic>low power design</topic><topic>multi-objective optimization</topic><topic>Optimization</topic><topic>Schedules</topic><topic>System level design</topic><toplevel>online_resources</toplevel><creatorcontrib>Ram, D. S. H.</creatorcontrib><creatorcontrib>Bhuvaneswari, M. C.</creatorcontrib><creatorcontrib>Logesh, S. M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ram, D. S. H.</au><au>Bhuvaneswari, M. C.</au><au>Logesh, S. M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths</atitle><btitle>2011 IEEE Computer Society Annual Symposium on VLSI</btitle><stitle>isvlsi</stitle><date>2011-07</date><risdate>2011</risdate><spage>290</spage><epage>295</epage><pages>290-295</pages><issn>2159-3469</issn><eissn>2159-3477</eissn><isbn>9781457708039</isbn><isbn>1457708035</isbn><eisbn>9780769544472</eisbn><eisbn>0769544479</eisbn><abstract>The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology for area, power and delay optimization using the Non-dominated Sorting Genetic Algorithm II (NSGA II). A metric based technique has been used to determine the likelihood of a schedule to yield low power solutions during binding. Actual power numbers are not determined since this is computationally expensive. The methodology has been evaluated on standard benchmark Data-Flow Graphs (DFGs) and results indicate that it yields improved solutions with better diversity when compared to a weighted sum GA approach. For the IIR benchmark, it was observed that the NSGA II was able to converge to the true Pareto front obtained from exhaustive search.</abstract><pub>IEEE</pub><doi>10.1109/ISVLSI.2011.55</doi><tpages>6</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 2159-3469 |
ispartof | 2011 IEEE Computer Society Annual Symposium on VLSI, 2011, p.290-295 |
issn | 2159-3469 2159-3477 |
language | eng |
recordid | cdi_ieee_primary_5992521 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Behavioral synthesis Benchmark testing Biological cells Delay evolutionary computation Genetic algorithms high-level synthesis low power design multi-objective optimization Optimization Schedules System level design |
title | A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T07%3A39%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20Novel%20Evolutionary%20Technique%20for%20Multi-objective%20Power,%20Area%20and%20Delay%20Optimization%20in%20High%20Level%20Synthesis%20of%20Datapaths&rft.btitle=2011%20IEEE%20Computer%20Society%20Annual%20Symposium%20on%20VLSI&rft.au=Ram,%20D.%20S.%20H.&rft.date=2011-07&rft.spage=290&rft.epage=295&rft.pages=290-295&rft.issn=2159-3469&rft.eissn=2159-3477&rft.isbn=9781457708039&rft.isbn_list=1457708035&rft_id=info:doi/10.1109/ISVLSI.2011.55&rft.eisbn=9780769544472&rft.eisbn_list=0769544479&rft_dat=%3Cieee_6IE%3E5992521%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-152f153bcd5b9740ec948d3f76460d7d483179ae55527bfa8a6ebad9941f78b83%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5992521&rfr_iscdi=true |