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Pinned to the walls - Impact of packaging and application properties on the memory and power walls
This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance co...
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| creator | Stanley-Marbell, P. Cabezas, V. C. Luijten, R. P. |
| description | This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance counter measurements of 25 applications. It is shown that if trends in supply pin count (growing as the square root of current) and total packaging pin count (doubling every six years) continue, application memory bandwidth requirements, even in the presence of aggressive cache hierarchies, may limit the number of on-chip threads to under a thousand in 2020. |
| doi_str_mv | 10.1109/ISLPED.2011.5993603 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5993603</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5993603</ieee_id><sourcerecordid>5993603</sourcerecordid><originalsourceid>FETCH-LOGICAL-i156t-fae9d574a814e4ac24fc8ea77674295f356956c7ea10071fc0872f50641048443</originalsourceid><addsrcrecordid>eNpVkM1Kw0AUhUdEUGqeoJt5gcS5yfwupVYNBCyo63JN7tTR_AxJoPTtrbYbz-Zw4JxvcRhbgsgAhLsrX6vN-iHLBUCmnCu0KC5Y4owFDbmVWjlx-S_b4pol0_QljtLaOQE37GMT-p4aPg98_iS-x7adeMrLLmI988Hzo3_jLvQ7jn3DMcY21DiHoedxHCKNc6CJH9PvuqNuGA9_xTjsaTzhbtmVx3ai5OwL9v64fls9p9XLU7m6r9IASs-pR3KNMhItSJJY59LXltAYbWTulC-UdkrXhhCEMOBrYU3uldAShLRSFgu2PHEDEW3jGDocD9vzM8UPL7BW1w</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Pinned to the walls - Impact of packaging and application properties on the memory and power walls</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Stanley-Marbell, P. ; Cabezas, V. C. ; Luijten, R. P.</creator><creatorcontrib>Stanley-Marbell, P. ; Cabezas, V. C. ; Luijten, R. P.</creatorcontrib><description>This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance counter measurements of 25 applications. It is shown that if trends in supply pin count (growing as the square root of current) and total packaging pin count (doubling every six years) continue, application memory bandwidth requirements, even in the presence of aggressive cache hierarchies, may limit the number of on-chip threads to under a thousand in 2020.</description><identifier>ISBN: 9781612846583</identifier><identifier>ISBN: 1612846580</identifier><identifier>EISBN: 9781612846590</identifier><identifier>EISBN: 9781612846606</identifier><identifier>EISBN: 1612846602</identifier><identifier>EISBN: 1612846599</identifier><identifier>DOI: 10.1109/ISLPED.2011.5993603</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>Bandwidth ; Clocks ; Hardware ; Instruction sets ; Memory management ; Pins ; System-on-a-chip</subject><ispartof>IEEE/ACM International Symposium on Low Power Electronics and Design, 2011, p.51-56</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5993603$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5993603$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Stanley-Marbell, P.</creatorcontrib><creatorcontrib>Cabezas, V. C.</creatorcontrib><creatorcontrib>Luijten, R. P.</creatorcontrib><title>Pinned to the walls - Impact of packaging and application properties on the memory and power walls</title><title>IEEE/ACM International Symposium on Low Power Electronics and Design</title><addtitle>ISLPED</addtitle><description>This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance counter measurements of 25 applications. It is shown that if trends in supply pin count (growing as the square root of current) and total packaging pin count (doubling every six years) continue, application memory bandwidth requirements, even in the presence of aggressive cache hierarchies, may limit the number of on-chip threads to under a thousand in 2020.</description><subject>Bandwidth</subject><subject>Clocks</subject><subject>Hardware</subject><subject>Instruction sets</subject><subject>Memory management</subject><subject>Pins</subject><subject>System-on-a-chip</subject><isbn>9781612846583</isbn><isbn>1612846580</isbn><isbn>9781612846590</isbn><isbn>9781612846606</isbn><isbn>1612846602</isbn><isbn>1612846599</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVkM1Kw0AUhUdEUGqeoJt5gcS5yfwupVYNBCyo63JN7tTR_AxJoPTtrbYbz-Zw4JxvcRhbgsgAhLsrX6vN-iHLBUCmnCu0KC5Y4owFDbmVWjlx-S_b4pol0_QljtLaOQE37GMT-p4aPg98_iS-x7adeMrLLmI988Hzo3_jLvQ7jn3DMcY21DiHoedxHCKNc6CJH9PvuqNuGA9_xTjsaTzhbtmVx3ai5OwL9v64fls9p9XLU7m6r9IASs-pR3KNMhItSJJY59LXltAYbWTulC-UdkrXhhCEMOBrYU3uldAShLRSFgu2PHEDEW3jGDocD9vzM8UPL7BW1w</recordid><startdate>201108</startdate><enddate>201108</enddate><creator>Stanley-Marbell, P.</creator><creator>Cabezas, V. C.</creator><creator>Luijten, R. P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201108</creationdate><title>Pinned to the walls - Impact of packaging and application properties on the memory and power walls</title><author>Stanley-Marbell, P. ; Cabezas, V. C. ; Luijten, R. P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i156t-fae9d574a814e4ac24fc8ea77674295f356956c7ea10071fc0872f50641048443</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2011</creationdate><topic>Bandwidth</topic><topic>Clocks</topic><topic>Hardware</topic><topic>Instruction sets</topic><topic>Memory management</topic><topic>Pins</topic><topic>System-on-a-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Stanley-Marbell, P.</creatorcontrib><creatorcontrib>Cabezas, V. C.</creatorcontrib><creatorcontrib>Luijten, R. P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Stanley-Marbell, P.</au><au>Cabezas, V. C.</au><au>Luijten, R. P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Pinned to the walls - Impact of packaging and application properties on the memory and power walls</atitle><btitle>IEEE/ACM International Symposium on Low Power Electronics and Design</btitle><stitle>ISLPED</stitle><date>2011-08</date><risdate>2011</risdate><spage>51</spage><epage>56</epage><pages>51-56</pages><isbn>9781612846583</isbn><isbn>1612846580</isbn><eisbn>9781612846590</eisbn><eisbn>9781612846606</eisbn><eisbn>1612846602</eisbn><eisbn>1612846599</eisbn><abstract>This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance counter measurements of 25 applications. It is shown that if trends in supply pin count (growing as the square root of current) and total packaging pin count (doubling every six years) continue, application memory bandwidth requirements, even in the presence of aggressive cache hierarchies, may limit the number of on-chip threads to under a thousand in 2020.</abstract><pub>IEEE</pub><doi>10.1109/ISLPED.2011.5993603</doi><tpages>6</tpages></addata></record> |
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| identifier | ISBN: 9781612846583 |
| ispartof | IEEE/ACM International Symposium on Low Power Electronics and Design, 2011, p.51-56 |
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| language | eng ; jpn |
| recordid | cdi_ieee_primary_5993603 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bandwidth Clocks Hardware Instruction sets Memory management Pins System-on-a-chip |
| title | Pinned to the walls - Impact of packaging and application properties on the memory and power walls |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T12%3A47%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Pinned%20to%20the%20walls%20-%20Impact%20of%20packaging%20and%20application%20properties%20on%20the%20memory%20and%20power%20walls&rft.btitle=IEEE/ACM%20International%20Symposium%20on%20Low%20Power%20Electronics%20and%20Design&rft.au=Stanley-Marbell,%20P.&rft.date=2011-08&rft.spage=51&rft.epage=56&rft.pages=51-56&rft.isbn=9781612846583&rft.isbn_list=1612846580&rft_id=info:doi/10.1109/ISLPED.2011.5993603&rft.eisbn=9781612846590&rft.eisbn_list=9781612846606&rft.eisbn_list=1612846602&rft.eisbn_list=1612846599&rft_dat=%3Cieee_6IE%3E5993603%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i156t-fae9d574a814e4ac24fc8ea77674295f356956c7ea10071fc0872f50641048443%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5993603&rfr_iscdi=true |