Total-dose worst-case test vectors for logic faults induced in combinational circuits of cell-based ASICs

We developed a methodology for identifying worst-case test vectors for logic faults induced in combinational circuits of cell-based ASICs induced by total dose. This methodology is independent of the design tools and the process technology.

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Bibliographic Details
Main Authors: Abou-Auf, Ahmed A., Abdel-Aziz, H. A., Abdel-Aziz, M. M.
Format: Conference Proceeding
Language:English
Subjects:
CMOS
logic faults
test vectors
total dose
worst-case
Online Access:Request full text
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Description
Summary:We developed a methodology for identifying worst-case test vectors for logic faults induced in combinational circuits of cell-based ASICs induced by total dose. This methodology is independent of the design tools and the process technology.
ISSN:0379-6566
DOI:10.1109/RADECS.2009.5994669