SEE evaluation of a low-power 1μm-SOI 80C51 for extremely harsh environments

• Main Authors: Manet, P., Falmagne, S., Garnier, J., Berger, G., Legat, J.-D
• Format: Conference Proceeding
• Language: English
• Subjects: Clocks; heavy ion irradiation; low power; Microcontrollers; Microprocessors; Power demand; Radiation effects; Radiation hardening; Random access memory; silicon on insulator; single event upset
• ISSN: 0379-6566
• DOI: 10.1109/RADECS.2009.5994718

In this paper, we present the SEE characterization of an 80C51 microcontroller optimized for high temperature and low-power applications. Its microarchitecture has been completely redesigned with deep low-power optimizations. It has been manufactured in a 1μm SOI process with tungsten metallization layers ensuring a high sustained operating temperature of 225°C. The SEE characterization presented here have been carried out in the Cyclotron Research Centre of Louvain-la-Neuve. It shows a very high threshold LET of 90 MeV/mg/cm 2 at a nominal Vdd of 5 V, while it is latchup immune due to SOI. Thanks to the power-optimized microarchitecture, its power consumption is only 8.5 mW/MIPS, which is close to a LEON2 FT manufactured in a far more sensitive 0.18μm process, making it a very low-power 80C51 for extremely harsh environments. Hardening by using a harsh process allows to use standard design tools and advanced aggressive low-power techniques. Even if the SOI 1μm technology used here is very big, results obtained in this work show that it can compete for low-power microcontrollers with a 0.18μm sub-micron technology hardened by using power hungry tripple modular redundancy. Whereas this harsh process approach offers quite better SEE tolerance.