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Equivalence Checking in Information System Hardware Design
Equivalence checking is playing a significant role in Intelligent Circuits design. However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on...
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creator | Fan Dehui Ma Guangsheng |
description | Equivalence checking is playing a significant role in Intelligent Circuits design. However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on WGL we give an algorithm for checking. Comparing the model WLDDs, the experiments show that the WGL is more efficient. |
doi_str_mv | 10.1109/ICMSS.2011.5999175 |
format | conference_proceeding |
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However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on WGL we give an algorithm for checking. Comparing the model WLDDs, the experiments show that the WGL is more efficient.</description><subject>Boolean functions</subject><subject>Circuit synthesis</subject><subject>Computational modeling</subject><subject>Delay</subject><subject>Design automation</subject><subject>Integrated circuit modeling</subject><subject>Polynomials</subject><isbn>1424465796</isbn><isbn>9781424465798</isbn><isbn>1424465818</isbn><isbn>142446580X</isbn><isbn>9781424465804</isbn><isbn>9781424465811</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9jrsOgjAYRmuMiTdeQJe-gNgfudUVNTA44U4a_MEqFG1Rw9vrQBz9lpOTs3yELIDZAIyvk-iYprbDAGyPcw6BNyBTcB3X9b0QwuFPAu6PiWXMlX3n-5wzPiHb_eMpX6JClSONLpjfpCqpVDRRRaNr0cpG0bQzLdY0Fvr8FhrpDo0s1ZyMClEZtHrOyPKwP0XxSiJidteyFrrL-k-b__UDO1Q5IQ</recordid><startdate>201108</startdate><enddate>201108</enddate><creator>Fan Dehui</creator><creator>Ma Guangsheng</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201108</creationdate><title>Equivalence Checking in Information System Hardware Design</title><author>Fan Dehui ; Ma Guangsheng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_59991753</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Boolean functions</topic><topic>Circuit synthesis</topic><topic>Computational modeling</topic><topic>Delay</topic><topic>Design automation</topic><topic>Integrated circuit modeling</topic><topic>Polynomials</topic><toplevel>online_resources</toplevel><creatorcontrib>Fan Dehui</creatorcontrib><creatorcontrib>Ma Guangsheng</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fan Dehui</au><au>Ma Guangsheng</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Equivalence Checking in Information System Hardware Design</atitle><btitle>2011 International Conference on Management and Service Science</btitle><stitle>ICMSS</stitle><date>2011-08</date><risdate>2011</risdate><spage>1</spage><epage>3</epage><pages>1-3</pages><isbn>1424465796</isbn><isbn>9781424465798</isbn><eisbn>1424465818</eisbn><eisbn>142446580X</eisbn><eisbn>9781424465804</eisbn><eisbn>9781424465811</eisbn><abstract>Equivalence checking is playing a significant role in Intelligent Circuits design. However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on WGL we give an algorithm for checking. Comparing the model WLDDs, the experiments show that the WGL is more efficient.</abstract><pub>IEEE</pub><doi>10.1109/ICMSS.2011.5999175</doi></addata></record> |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Boolean functions Circuit synthesis Computational modeling Delay Design automation Integrated circuit modeling Polynomials |
title | Equivalence Checking in Information System Hardware Design |
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