Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs

• Main Authors: Shuli Gao, Al-Khalili, D., Chabini, N.
• Format: Conference Proceeding
• Language: English
• Subjects: Adders; Computer architecture; Delay; Digital signal processing; Educational institutions; Field programmable gate arrays; Organizations
• ISSN: 1530-2075
• DOI: 10.1109/IPDPS.2011.152

In this paper, asymmetric non-pipelined large size signed multipliers are implemented using symmetric and asymmetric embedded multipliers in FPGAs. Decomposition of the operands, and consequently the multiplication process, are performed for the efficient use of the embedded blocks. Partial products are organized in various configurations, and the additions of the products are performed in an optimized manner. A heuristic method has been developed, which analyzes the timing and the area at each stage of the adder tree. The optimization algorithm, which is referred to as "Delay-Table" method has led to the minimization of the total critical path delay with reduced utilization of FPGA resources. The asymmetric signed multipliers are implemented in Xilinx FPGAs using 18×18-bit and 25×18-bit embedded signed multipliers. The implementation results have demonstrated an improvement in terms of speed and number of embedded blocks compared to the standard realization. The improvements are 27.1% in speed and 10.9% in the use of embedded multipliers when using the symmetric embedded blocks. The improvements increase further to 28.5% and 36.6%, respectively, when using asymmetric embedded multipliers.