A performance-power evaluation of FinFET flip-flops under process variations

In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock...

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Bibliographic Details
Main Authors: Munson, P. M., Delgado-Frias, J. G.
Format: Conference Proceeding
Language:English
Subjects:
Delay
double-gate MOSFET
FinFET
Flip-flop performance
Flip-flops
low power registers
Monte Carlo
register delay
Registers
USA Councils
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Summary:In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock to Q times (called register delay) are in the pipeline stage critical path. Our study shows that the Low Delay (LDFF) flip-flop has the shortest register delay of 5.7ps. The flip-flop with the lowest power consumption is LPFF with 17.4 μW. Our simulations were performed using the University of Florida UFDG: Double-Gate MOSFET Model through the interface of Spice3f5 and Ngspice (ngspice3.ufdg-3.7) and a 32nm technology.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2011.6026271