A performance-power evaluation of FinFET flip-flops under process variations

In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock...

Full description

Saved in:
Bibliographic Details
Main Authors: Munson, P. M., Delgado-Frias, J. G.
Format: Conference Proceeding
Language:English
Subjects:
Delay
double-gate MOSFET
FinFET
Flip-flop performance
Flip-flops
low power registers
Monte Carlo
register delay
Registers
USA Councils
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 4
container_issue
container_start_page 1
container_title
container_volume
creator Munson, P. M.
Delgado-Frias, J. G.
description In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock to Q times (called register delay) are in the pipeline stage critical path. Our study shows that the Low Delay (LDFF) flip-flop has the shortest register delay of 5.7ps. The flip-flop with the lowest power consumption is LPFF with 17.4 μW. Our simulations were performed using the University of Florida UFDG: Double-Gate MOSFET Model through the interface of Spice3f5 and Ngspice (ngspice3.ufdg-3.7) and a 32nm technology.
doi_str_mv 10.1109/MWSCAS.2011.6026271
format conference_proceeding
fullrecord <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_6026271</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6026271</ieee_id><sourcerecordid>6026271</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-e427ea944056b83584a8ba2368aff72394f18c7fdf6d022a474bd5f8b488abf23</originalsourceid><addsrcrecordid>eNo1kMtOwzAURM1Loi39gm78Awl--3oZRbQgBbEoiGXlJLZklCaR3Rbx9wQoq1mcM7MYhFaU5JQSc__8vi2Lbc4IpbkiTDFNL9CcKspAgNTyEs2olJBxMOYKLY2Gf6b49Q8TE9NC3aJ5Sh-EMK6pmaGqwKOLfoh72zcuG4dPF7E72e5oD2Ho8eDxOvTrh1fsuzBmvhvGhI99O1ljHBqXEj7ZGH7ldIduvO2SW55zgd6mZvmYVS-bp7KoskC1PGROMO2sEYJIVQOXICzUlnEF1nvNuBGeQqN961VLGLNCi7qVHmoBYGvP-AKt_naDc243xrC38Wt3foV_A4ILUsk</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A performance-power evaluation of FinFET flip-flops under process variations</title><source>IEEE Xplore All Conference Series</source><creator>Munson, P. M. ; Delgado-Frias, J. G.</creator><creatorcontrib>Munson, P. M. ; Delgado-Frias, J. G.</creatorcontrib><description>In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock to Q times (called register delay) are in the pipeline stage critical path. Our study shows that the Low Delay (LDFF) flip-flop has the shortest register delay of 5.7ps. The flip-flop with the lowest power consumption is LPFF with 17.4 μW. Our simulations were performed using the University of Florida UFDG: Double-Gate MOSFET Model through the interface of Spice3f5 and Ngspice (ngspice3.ufdg-3.7) and a 32nm technology.</description><identifier>ISSN: 1548-3746</identifier><identifier>ISBN: 9781612848563</identifier><identifier>ISBN: 1612848567</identifier><identifier>EISSN: 1558-3899</identifier><identifier>EISBN: 1612848575</identifier><identifier>EISBN: 9781612848570</identifier><identifier>EISBN: 9781612848556</identifier><identifier>EISBN: 1612848559</identifier><identifier>DOI: 10.1109/MWSCAS.2011.6026271</identifier><language>eng</language><publisher>IEEE</publisher><subject>Delay ; double-gate MOSFET ; FinFET ; Flip-flop performance ; Flip-flops ; low power registers ; Monte Carlo ; register delay ; Registers ; USA Councils</subject><ispartof>2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6026271$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6026271$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Munson, P. M.</creatorcontrib><creatorcontrib>Delgado-Frias, J. G.</creatorcontrib><title>A performance-power evaluation of FinFET flip-flops under process variations</title><title>2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)</title><addtitle>MWSCAS</addtitle><description>In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock to Q times (called register delay) are in the pipeline stage critical path. Our study shows that the Low Delay (LDFF) flip-flop has the shortest register delay of 5.7ps. The flip-flop with the lowest power consumption is LPFF with 17.4 μW. Our simulations were performed using the University of Florida UFDG: Double-Gate MOSFET Model through the interface of Spice3f5 and Ngspice (ngspice3.ufdg-3.7) and a 32nm technology.</description><subject>Delay</subject><subject>double-gate MOSFET</subject><subject>FinFET</subject><subject>Flip-flop performance</subject><subject>Flip-flops</subject><subject>low power registers</subject><subject>Monte Carlo</subject><subject>register delay</subject><subject>Registers</subject><subject>USA Councils</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>9781612848563</isbn><isbn>1612848567</isbn><isbn>1612848575</isbn><isbn>9781612848570</isbn><isbn>9781612848556</isbn><isbn>1612848559</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kMtOwzAURM1Loi39gm78Awl--3oZRbQgBbEoiGXlJLZklCaR3Rbx9wQoq1mcM7MYhFaU5JQSc__8vi2Lbc4IpbkiTDFNL9CcKspAgNTyEs2olJBxMOYKLY2Gf6b49Q8TE9NC3aJ5Sh-EMK6pmaGqwKOLfoh72zcuG4dPF7E72e5oD2Ho8eDxOvTrh1fsuzBmvhvGhI99O1ljHBqXEj7ZGH7ldIduvO2SW55zgd6mZvmYVS-bp7KoskC1PGROMO2sEYJIVQOXICzUlnEF1nvNuBGeQqN961VLGLNCi7qVHmoBYGvP-AKt_naDc243xrC38Wt3foV_A4ILUsk</recordid><startdate>201108</startdate><enddate>201108</enddate><creator>Munson, P. M.</creator><creator>Delgado-Frias, J. G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201108</creationdate><title>A performance-power evaluation of FinFET flip-flops under process variations</title><author>Munson, P. M. ; Delgado-Frias, J. G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-e427ea944056b83584a8ba2368aff72394f18c7fdf6d022a474bd5f8b488abf23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Delay</topic><topic>double-gate MOSFET</topic><topic>FinFET</topic><topic>Flip-flop performance</topic><topic>Flip-flops</topic><topic>low power registers</topic><topic>Monte Carlo</topic><topic>register delay</topic><topic>Registers</topic><topic>USA Councils</topic><toplevel>online_resources</toplevel><creatorcontrib>Munson, P. M.</creatorcontrib><creatorcontrib>Delgado-Frias, J. G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Munson, P. M.</au><au>Delgado-Frias, J. G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A performance-power evaluation of FinFET flip-flops under process variations</atitle><btitle>2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)</btitle><stitle>MWSCAS</stitle><date>2011-08</date><risdate>2011</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>9781612848563</isbn><isbn>1612848567</isbn><eisbn>1612848575</eisbn><eisbn>9781612848570</eisbn><eisbn>9781612848556</eisbn><eisbn>1612848559</eisbn><abstract>In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock to Q times (called register delay) are in the pipeline stage critical path. Our study shows that the Low Delay (LDFF) flip-flop has the shortest register delay of 5.7ps. The flip-flop with the lowest power consumption is LPFF with 17.4 μW. Our simulations were performed using the University of Florida UFDG: Double-Gate MOSFET Model through the interface of Spice3f5 and Ngspice (ngspice3.ufdg-3.7) and a 32nm technology.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2011.6026271</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1548-3746
ispartof 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4
issn 1548-3746
1558-3899
language eng
recordid cdi_ieee_primary_6026271
source IEEE Xplore All Conference Series
subjects Delay
double-gate MOSFET
FinFET
Flip-flop performance
Flip-flops
low power registers
Monte Carlo
register delay
Registers
USA Councils
title A performance-power evaluation of FinFET flip-flops under process variations
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T19%3A07%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20performance-power%20evaluation%20of%20FinFET%20flip-flops%20under%20process%20variations&rft.btitle=2011%20IEEE%2054th%20International%20Midwest%20Symposium%20on%20Circuits%20and%20Systems%20(MWSCAS)&rft.au=Munson,%20P.%20M.&rft.date=2011-08&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.issn=1548-3746&rft.eissn=1558-3899&rft.isbn=9781612848563&rft.isbn_list=1612848567&rft_id=info:doi/10.1109/MWSCAS.2011.6026271&rft.eisbn=1612848575&rft.eisbn_list=9781612848570&rft.eisbn_list=9781612848556&rft.eisbn_list=1612848559&rft_dat=%3Cieee_CHZPO%3E6026271%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-e427ea944056b83584a8ba2368aff72394f18c7fdf6d022a474bd5f8b488abf23%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6026271&rfr_iscdi=true