Offset voltage analysis of dynamic latched comparator

The offset voltage of the dynamic latched comparator is analyzed in detail, and the dynamic latched comparator design is optimized for the minimal offset voltage based on the analysis in this paper. As a result, 1-sigma offset voltage was reduced from 12.5mV to 6.5mV at the cost of 9% increase of th...

Full description

Saved in:
Bibliographic Details
Main Authors: HeungJun Jeon, Yong-Bin Kim, Minsu Choi
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The offset voltage of the dynamic latched comparator is analyzed in detail, and the dynamic latched comparator design is optimized for the minimal offset voltage based on the analysis in this paper. As a result, 1-sigma offset voltage was reduced from 12.5mV to 6.5mV at the cost of 9% increase of the power dissipation (152μW from 136μW). Using a digitally controlled capacitive offset calibration technique, the offset voltage of the comparator is further reduced from 6.50mV to 1.10mV at 1-sigma at the operating clock frequency of 3GHz and it consumes 54μW/GHz after the calibration.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2011.6026358