A signal integrity enhancement technique for high speed test systems

Signal integrity degradation at high frequencies affects test results and increases the yield loss of integrated circuits. Parasitic effects and electromagnetic coupling due to transmission lines degrade the integrity of test signals and undermine the accuracy of the measurement results. A new signa...

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Bibliographic Details
Main Authors: Kandalaft, N., Rashidzadeh, R., Ahmadi, M.
Format: Conference Proceeding
Language:English
Subjects:
Automatic test equipment
Degradation
Device under test
Integrated circuit modeling
Lead
Power cables
Proportional-Integrator-differentiator (PID)
RLC circuits
signal integrity
transmission line
Transmission line measurements
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Summary:Signal integrity degradation at high frequencies affects test results and increases the yield loss of integrated circuits. Parasitic effects and electromagnetic coupling due to transmission lines degrade the integrity of test signals and undermine the accuracy of the measurement results. A new signal integrity enhancement technique is presented in this paper to compensate the signal loss. A Proportional Integrator-Differentiator (PID) circuit is implemented as an overshoot generator to negate the undesired effects of transmission lines. Simulation results at 1GHz show that the proposed method can improve the rise and fall time by orders of magnitude, and increase the eye-opening by more than 40%.
ISSN:0840-7789
2576-7046
DOI:10.1109/CCECE.2011.6030674