Loading…
Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET
In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demon...
Saved in:
Published in: | IEEE transactions on electron devices 2011-11, Vol.58 (11), p.3793-3800 |
---|---|
Main Authors: | , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | cdi_FETCH-LOGICAL-c306t-62b4cab4785f43b8349c8fb07466695d2c3a176b147e3453c49d4f2ccf1570623 |
container_end_page | 3800 |
container_issue | 11 |
container_start_page | 3793 |
container_title | IEEE transactions on electron devices |
container_volume | 58 |
creator | Valentin, R. Bertrand, G. Puget, S. Scheer, P. Juge, A. Jaouen, H. Raynaud, C. |
description | In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak GM and C GG as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs. |
doi_str_mv | 10.1109/TED.2011.2165283 |
format | article |
fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_ieee_primary_6032736</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6032736</ieee_id><sourcerecordid>2491696301</sourcerecordid><originalsourceid>FETCH-LOGICAL-c306t-62b4cab4785f43b8349c8fb07466695d2c3a176b147e3453c49d4f2ccf1570623</originalsourceid><addsrcrecordid>eNpdkEtLAzEUhYMoWB97wc0gCG6mJrl5TJa11geoFVpxGTKZBKdMZ2oyRfrvTWlx4epyz_3O4XIQuiB4SAhWt_PJ_ZBiQoaUCE4LOEADwrnMlWDiEA0wJkWuoIBjdBLjIq2CMTpAozcTQveTf9ZV_5VNvHe2j1nXZia766pNPq9dlb2b0NemaTbZvVs1rk_SbPqcvU5nD5P5GTryponufD9P0UdSx0_5y_TxeTx6yS1g0eeClsyaksmCewZlAUzZwpdYMiGE4hW1YIgUJWHSAeNgmaqYp9Z6wiUWFE7RzS53FbrvtYu9XtbRuqYxrevWUZOUyCgBxRJ69Q9ddOvQpu-0whhzCaAShHeQDV2MwXm9CvXShI0mWG8r1alSva1U7ytNlut9ronWND6Y1tbxz0eZlILwbfTljqudc39ngYFKEPALr9d6zA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>900057339</pqid></control><display><type>article</type><title>Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Valentin, R. ; Bertrand, G. ; Puget, S. ; Scheer, P. ; Juge, A. ; Jaouen, H. ; Raynaud, C.</creator><creatorcontrib>Valentin, R. ; Bertrand, G. ; Puget, S. ; Scheer, P. ; Juge, A. ; Jaouen, H. ; Raynaud, C.</creatorcontrib><description>In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak GM and C GG as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2011.2165283</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>65 nm ; Applied sciences ; Body contact ; body tied ; Contact ; Contacts ; Depletion ; Electronics ; Exact sciences and technology ; Gates ; Logic gates ; Mathematical analysis ; MOSFET ; MOSFET circuits ; MOSFETs ; narrow-width effects (NWEs) ; partially depleted (PD) ; Semiconductor devices ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Shape ; Silicon on insulator technology ; silicon-on-insulator (SOI) ; Topology ; Transistors</subject><ispartof>IEEE transactions on electron devices, 2011-11, Vol.58 (11), p.3793-3800</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nov 2011</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c306t-62b4cab4785f43b8349c8fb07466695d2c3a176b147e3453c49d4f2ccf1570623</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6032736$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=24776159$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Valentin, R.</creatorcontrib><creatorcontrib>Bertrand, G.</creatorcontrib><creatorcontrib>Puget, S.</creatorcontrib><creatorcontrib>Scheer, P.</creatorcontrib><creatorcontrib>Juge, A.</creatorcontrib><creatorcontrib>Jaouen, H.</creatorcontrib><creatorcontrib>Raynaud, C.</creatorcontrib><title>Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak GM and C GG as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.</description><subject>65 nm</subject><subject>Applied sciences</subject><subject>Body contact</subject><subject>body tied</subject><subject>Contact</subject><subject>Contacts</subject><subject>Depletion</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gates</subject><subject>Logic gates</subject><subject>Mathematical analysis</subject><subject>MOSFET</subject><subject>MOSFET circuits</subject><subject>MOSFETs</subject><subject>narrow-width effects (NWEs)</subject><subject>partially depleted (PD)</subject><subject>Semiconductor devices</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Shape</subject><subject>Silicon on insulator technology</subject><subject>silicon-on-insulator (SOI)</subject><subject>Topology</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><recordid>eNpdkEtLAzEUhYMoWB97wc0gCG6mJrl5TJa11geoFVpxGTKZBKdMZ2oyRfrvTWlx4epyz_3O4XIQuiB4SAhWt_PJ_ZBiQoaUCE4LOEADwrnMlWDiEA0wJkWuoIBjdBLjIq2CMTpAozcTQveTf9ZV_5VNvHe2j1nXZia766pNPq9dlb2b0NemaTbZvVs1rk_SbPqcvU5nD5P5GTryponufD9P0UdSx0_5y_TxeTx6yS1g0eeClsyaksmCewZlAUzZwpdYMiGE4hW1YIgUJWHSAeNgmaqYp9Z6wiUWFE7RzS53FbrvtYu9XtbRuqYxrevWUZOUyCgBxRJ69Q9ddOvQpu-0whhzCaAShHeQDV2MwXm9CvXShI0mWG8r1alSva1U7ytNlut9ronWND6Y1tbxz0eZlILwbfTljqudc39ngYFKEPALr9d6zA</recordid><startdate>20111101</startdate><enddate>20111101</enddate><creator>Valentin, R.</creator><creator>Bertrand, G.</creator><creator>Puget, S.</creator><creator>Scheer, P.</creator><creator>Juge, A.</creator><creator>Jaouen, H.</creator><creator>Raynaud, C.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20111101</creationdate><title>Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET</title><author>Valentin, R. ; Bertrand, G. ; Puget, S. ; Scheer, P. ; Juge, A. ; Jaouen, H. ; Raynaud, C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c306t-62b4cab4785f43b8349c8fb07466695d2c3a176b147e3453c49d4f2ccf1570623</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>65 nm</topic><topic>Applied sciences</topic><topic>Body contact</topic><topic>body tied</topic><topic>Contact</topic><topic>Contacts</topic><topic>Depletion</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gates</topic><topic>Logic gates</topic><topic>Mathematical analysis</topic><topic>MOSFET</topic><topic>MOSFET circuits</topic><topic>MOSFETs</topic><topic>narrow-width effects (NWEs)</topic><topic>partially depleted (PD)</topic><topic>Semiconductor devices</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Shape</topic><topic>Silicon on insulator technology</topic><topic>silicon-on-insulator (SOI)</topic><topic>Topology</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Valentin, R.</creatorcontrib><creatorcontrib>Bertrand, G.</creatorcontrib><creatorcontrib>Puget, S.</creatorcontrib><creatorcontrib>Scheer, P.</creatorcontrib><creatorcontrib>Juge, A.</creatorcontrib><creatorcontrib>Jaouen, H.</creatorcontrib><creatorcontrib>Raynaud, C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library Online</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Valentin, R.</au><au>Bertrand, G.</au><au>Puget, S.</au><au>Scheer, P.</au><au>Juge, A.</au><au>Jaouen, H.</au><au>Raynaud, C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2011-11-01</date><risdate>2011</risdate><volume>58</volume><issue>11</issue><spage>3793</spage><epage>3800</epage><pages>3793-3800</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak GM and C GG as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2011.2165283</doi><tpages>8</tpages></addata></record> |
fulltext | fulltext |
identifier | ISSN: 0018-9383 |
ispartof | IEEE transactions on electron devices, 2011-11, Vol.58 (11), p.3793-3800 |
issn | 0018-9383 1557-9646 |
language | eng |
recordid | cdi_ieee_primary_6032736 |
source | IEEE Electronic Library (IEL) Journals |
subjects | 65 nm Applied sciences Body contact body tied Contact Contacts Depletion Electronics Exact sciences and technology Gates Logic gates Mathematical analysis MOSFET MOSFET circuits MOSFETs narrow-width effects (NWEs) partially depleted (PD) Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Shape Silicon on insulator technology silicon-on-insulator (SOI) Topology Transistors |
title | Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T00%3A03%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Narrow-Width%20Effects%20on%20a%20Body-Tied%20Partially%20Depleted%20SOI%20MOSFET&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Valentin,%20R.&rft.date=2011-11-01&rft.volume=58&rft.issue=11&rft.spage=3793&rft.epage=3800&rft.pages=3793-3800&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2011.2165283&rft_dat=%3Cproquest_ieee_%3E2491696301%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c306t-62b4cab4785f43b8349c8fb07466695d2c3a176b147e3453c49d4f2ccf1570623%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=900057339&rft_id=info:pmid/&rft_ieee_id=6032736&rfr_iscdi=true |