A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 μm 2 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V VDD MIN operation is enabled by three assist features. Stability is improved by a bit-line regulation scheme which reduce...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2012-01, Vol.47 (1), p.97-106
Main Authors: Pilo, H., Arsovski, I., Batson, K., Braceras, G., Gabric, J., Houle, R., Lamphier, S., Radens, C., Seferagic, A.
Format: Article
Language:English
Subjects:
32 nm
Applied sciences
Circuit stability
CMOS memory integrated circuits
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
high-k metal-gate
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic gates
Random access memory
read assist
Regulators
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Stability analysis
stability assist
static random-access memory (SRAM)
Thermal stability
Vddmin
Voltage control
write assist
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Summary:A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 μm 2 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V VDD MIN operation is enabled by three assist features. Stability is improved by a bit-line regulation scheme which reduces charge injection into the bit-cell. Enhancements to the write path include an increase of 40% of bit-line boost voltage. Finally, a bit-cell-tracking delay circuit improves both performance and yield across the process space.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2011.2164730