A class-AB flipped voltage follower output stage

In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing...

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Bibliographic Details
Main Authors: Centurelli, F., Monsurro, P., Trifiletti, A.
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
class-AB
CMOS integrated circuits
flipped voltage follower
Gain
Linearity
Logic gates
low power design
output stage
Resistance
Topology
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Summary:In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage low-power stages requiring low bias currents but driving large capacitive loads with large signal swing. These buffers have been compared using 65nm CMOS technology models provided by STMicroelectronics. The buffer consumes 10μA from a 1.2V supply, and has a bandwidth of 100MHz with a 2pF load. It has -50dB HD2 and -60dB HD3 when the input is a 0.5VPP sinusoid at 1MHz, and the 1% settling time to a 0.5V PP square wave is about 20ns.
DOI:10.1109/ECCTD.2011.6043851