Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)

New 4F 2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static m...

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Bibliographic Details
Main Authors: Hyunwoo Chung, Huijung Kim, Hyungi Kim, Kanguk Kim, Sua Kim, Ki-Whan Song, Jiyoung Kim, Yong Chul Oh, Yoosang Hwang, Hyeongsun Hong, Gyo-Young Jin, Chilhee Chung
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Junctions
Logic gates
Microprocessors
Random access memory
Silicon
Transistors
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Summary:New 4F 2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F 2 and 6F 2 cells.
ISSN:1930-8876
DOI:10.1109/ESSDERC.2011.6044197